Just fell down a rabbit hole on spin-valley physics in silicon spin qubits and had an idea I can’t shake: what if we intentionally operate at spin-valley anticrossings to create a “clock transition” style qubit that’s first-order insensitive to electric field noise, but still EDSR-addressable?

As I understand it, near the spin-valley mixing point (where Zeeman ≈ valley splitting), the qubit frequency’s slope versus gate voltage can flatten dramatically. That sounds like a built‑in sweet spot against charge noise, a bit like donor clock transitions or transmon sweet spots, but in a silicon quantum dot. It also seems like the same mixing enables strong electrically driven spin resonance. Has anyone tried to systematically design for this regime across an array, rather than avoiding it?

Questions I’m super curious about:

Valley splitting engineering: What knobs are actually precise enough in practice to pin valley splitting device‑to‑device so arrays can share a stable sweet spot? Interface steps, vertical electric field, local strain, SiGe composition, gate metals/work function, patterned stressors? Any process recipes that reduce valley variability below, say, 10% across a die?
Coherence trade‑offs: Do you get a measurable T2* boost near the spin-valley clock transition due to dω/dV ≈ 0, or do enhanced spin-phonon channels at the anticrossing just kill T1? Has anyone mapped T1 and T2* versus detuning from the mixing point with micromagnets on?
Micromagnet and drive design: Can micromagnet gradients be shaped to keep large Rabi rates without pushing the qubit frequency into a relaxation hotspot? Would narrowband on‑chip filters or high‑impedance resonators suppress radiative decay at the qubit frequency while still letting in strong drive power?
Two‑qubit gates: How ugly does exchange look when the logical qubit has appreciable valley character? Any hidden leakage channels or exchange dispersion that show up at the anticrossing? Can symmetric exchange sweet spots and spin-valley sweet spots coexist?
Readout near the mixing point: In double dots, does Pauli spin blockade become fragile as valley states mix? Any tips to keep high‑contrast latched readout or RF‑gate dispersive readout working near this regime?
Array‑level control: If qubit frequency becomes less tunable electrically at the sweet spot, is magnetic tuning or local ESR addressability the way forward? Or could we use two‑tone Raman‑like drives to get tunability without moving off the sweet spot?
Phononic/electromagnetic environment: Has anyone tried co‑designing a phononic bandgap (etched phononic crystal or acoustic Bragg stack under the channel) to suppress the specific phonon modes that open T1 at the anticrossing, while also adding on‑chip ESDR line filters to kill Purcell‑like loss?
Modeling and metrology: Any recommended simulators or compact models that include realistic interface disorder, strain, valley‑orbit coupling, and micromagnet fields to predict where the clock transition lands? Experimentally, what’s the cleanest protocol to locate and lock to the minimum dω/dV point in real time?

If this “valley clock transition” approach is viable, it feels like a neat path to both fast all‑electrical control and improved dephasing robustness in silicon-without needing to abandon CMOS‑friendly stacks. Curious if people have tried this deliberately, hit show‑stoppers, or have tricks to make it practical at scale.