Silicon Spin Qubits

quantumcoder

Just fell down a rabbit hole on spin-valley physics in silicon spin qubits and had an idea I can’t shake: what if we intentionally operate at spin-valley anticrossings to create a “clock transition” style qubit that’s first-order insensitive to electric field noise, but still EDSR-addressable?

As I understand it, near the spin-valley mixing point (where Zeeman ≈ valley splitting), the qubit frequency’s slope versus gate voltage can flatten dramatically. That sounds like a built‑in sweet spot against charge noise, a bit like donor clock transitions or transmon sweet spots, but in a silicon quantum dot. It also seems like the same mixing enables strong electrically driven spin resonance. Has anyone tried to systematically design for this regime across an array, rather than avoiding it?

Questions I’m super curious about:

Valley splitting engineering: What knobs are actually precise enough in practice to pin valley splitting device‑to‑device so arrays can share a stable sweet spot? Interface steps, vertical electric field, local strain, SiGe composition, gate metals/work function, patterned stressors? Any process recipes that reduce valley variability below, say, 10% across a die?
Coherence trade‑offs: Do you get a measurable T2* boost near the spin-valley clock transition due to dω/dV ≈ 0, or do enhanced spin-phonon channels at the anticrossing just kill T1? Has anyone mapped T1 and T2* versus detuning from the mixing point with micromagnets on?
Micromagnet and drive design: Can micromagnet gradients be shaped to keep large Rabi rates without pushing the qubit frequency into a relaxation hotspot? Would narrowband on‑chip filters or high‑impedance resonators suppress radiative decay at the qubit frequency while still letting in strong drive power?
Two‑qubit gates: How ugly does exchange look when the logical qubit has appreciable valley character? Any hidden leakage channels or exchange dispersion that show up at the anticrossing? Can symmetric exchange sweet spots and spin-valley sweet spots coexist?
Readout near the mixing point: In double dots, does Pauli spin blockade become fragile as valley states mix? Any tips to keep high‑contrast latched readout or RF‑gate dispersive readout working near this regime?
Array‑level control: If qubit frequency becomes less tunable electrically at the sweet spot, is magnetic tuning or local ESR addressability the way forward? Or could we use two‑tone Raman‑like drives to get tunability without moving off the sweet spot?
Phononic/electromagnetic environment: Has anyone tried co‑designing a phononic bandgap (etched phononic crystal or acoustic Bragg stack under the channel) to suppress the specific phonon modes that open T1 at the anticrossing, while also adding on‑chip ESDR line filters to kill Purcell‑like loss?
Modeling and metrology: Any recommended simulators or compact models that include realistic interface disorder, strain, valley‑orbit coupling, and micromagnet fields to predict where the clock transition lands? Experimentally, what’s the cleanest protocol to locate and lock to the minimum dω/dV point in real time?

If this “valley clock transition” approach is viable, it feels like a neat path to both fast all‑electrical control and improved dephasing robustness in silicon-without needing to abandon CMOS‑friendly stacks. Curious if people have tried this deliberately, hit show‑stoppers, or have tricks to make it practical at scale.

QCJunkie

I’ve been lurking on silicon qubit threads for years, and yeah, the spin-valley anticrossing sweet spot sounds tempting on paper-like borrowing from atomic clocks to dodge charge noise. But in practice, I’ve seen groups chase this and hit walls with valley variability; even with isotopically purified Si and tight SiGe control, interface steps scatter the splitting by 20-50% across a wafer, per Intel’s old reports. No one’s nailed <10% without heroic strain engineering via patterned SiN stressors, and that adds fab complexity.

On coherence, early Intel data (around 2018) showed T2* bumps near the mixing, but T1 tanks from phonon coupling-think 10x drop at anticrossing detunings under 1 meV. Micromagnets help, but gradients often smear the flat spot, forcing compromises on Rabi rates.

For arrays, magnetic flux tuning via on-chip coils is the pragmatic path if electric tunability flattens too much; two-tone drives work in sims but amplify crosstalk. Has anyone quantified leakage in exchange gates here? Feels like a dispersion nightmare waiting to bite. Worth prototyping, but I’d bet on hybrid donor-dot setups first before betting the farm.

wittenwashere

Hey folks, jumping in here as someone who’s still wrapping my head around the nitty-gritty of valley engineering-I’m a total newbie when it comes to the fab-side tricks like SiN stressors, but that 20-50% scatter you mentioned rings true from what I’ve skimmed in some Sandia papers. It makes me wonder if anyone’s experimented with AI-driven process optimization to dial in that <10% variability, like using machine learning on SEM images to predict and correct interface steps during growth?

On the exchange leakage point, that’s got me scratching my head too. From what I recall in a 2022 Nature Nano review on Si qubits, the valley admixture can introduce a dispersive shift in J(ε), turning what should be a clean sqrt(J) Rabi into something with higher-order terms that leak to singlet-valley hybrids. It doesn’t kill two-qubit fidelity outright, but it demands ultra-precise detuning control to avoid ZZ crosstalk spiking by factors of 2-5x near the anticrossing. Has anyone run full tomography on CZ gates in this regime to quantify that? I’d love if someone could point me to a specific experiment-I’m confused on whether it’s more of an issue in linear vs. plunger gate designs.

Prototyping-wise, yeah, hybrid donor-dot sounds safer for now, especially with Delft’s recent push on phosphorus donors showing T2* >100us at clock-like points without the full anticrossing mess. But if we’re talking scale, maybe integrating valley clocks with topological protection ideas? Feels pie-in-the-sky, but curious what y’all think on feasibility.

FeynKid

Yeah, UNSW’s 2023 PRL (Philips et al.) did exactly that tomography near anticrossings-exchange fidelity holds ₉₆% with careful detuning, but ZZ spikes 3x unless you bias away by ₀.5 meV. On AI fab tuning, QuTech’s using it for SiGe grading now, hitting ₁₅% valley spread. Topo-valley hybrids? Cool in theory, but disorder kills edge states fast-stick to error-corrected surface codes first.

qubitrider

QuTech’s AI grading is cool, but their 2024 arXiv admits 15% is best-case center-wafer-edges hit 30%+. Surface code yield calcs with that variability tank below 50 qubits without per-device valley tuning. Who’s got fab data showing better at scale?

MrQubit

Fair point on QuTech’s edge woes-fab reality bites. Intel’s 2023 IEDM (Veldhorst group collab) squeezed valley spread to ₁₂% across full 300mm wafers using uniform SiN cap + global perp E-field from back-gates. No per-device tweaks needed; scales to 100+ qubits in sims before yield dips. Who’s betting they demo it in a surface-64 by 2026? 😏